Arm booting process

Reset-> CPU Exectue the code located on address 0x0 ( volatile dynamic memory (ex: DRAM or SDRAM) ). The code is bootloader.


But in general, the code of bootloader is located in the non-volatile static memory (NOR or NAND flash). So the ARM-based system use one boot memory remap circuit (Users can use the switch to control the behavior of the circuit ) to let the non-volatile memory address of the bootloader remap to the boot address.

The following steps is the more detail process of booting process on ARM:

1. At reset, the remap signals are both high, therefore static memory is remapped to
address 0x0. Perform any critical CPU initialization at this time.
Ensure that you do not access SDRAM at this point as it has not been initialized.

2. For NOR flash 1 (nNORCS), jump to a location in the range
0x34000000–0x37FFFFFF. Jumping out of the range 0x000000000–0x03FFFFFF means
that the remapped memory at 0x0 is no longer needed and can be unmapped.

The code jumps to 0x34000000–0x37FFFFFF rather than the physical location of the
boot memory because the boot code does not know which physical memory
device it is located in and because the control registers for the other static memory
device selects are not installed.

The following process is finished in the bootloader:

3. Clear the DEVCHIP REMAP bit by writing a 1 to bit 8 of the System Controller
register at 0x101E0000. This removes the remapping of boot memory to 0x0.

4. Initialize the MPMC controller with the appropriate values for the type of
dynamic RAM used.

5. Use the SDRAM at location 0x0 to hold additional initialization code and the
stack for the application.

6. Jump to the initialization code in SDRAM.

7. Set up all static chip select control registers. If you are not booting from NOR
flash, you must also set up the control register for nSTATICCS1.

8. Clear the FPGA_REMAP signal by writing a 0 to bit 2 of SYS_MISC register.
This removes the remapping of memory to 0x34000000–0x37FFFFFF.


Reference:

(1) http://www.wretch.cc/blog/tomyam/12334577
(2) http://www.cnieee.com/mcu/MCUYJ/ARM/200804/789.html
(3) http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0411b/Cacddjje.html