DDR SDRAM NOTES

In this architecture, 2n bits of data are transferred from the memory cell array to the I/O buffer every clock cycle. Data transferred to the I/O buffer is output n bits at a time (even and odd addresses) every half-clock cycle. As a result, data is output continuously in synchronization with the rising and falling edges of the clock.

1. Internal bus width = 2*(bus width of data transfer at the I/O)

2. If the wiring length between the memory and the controller is different, the time
required for data to reach the receiver (flight time) is different. This makes it difficult for the receiver to determine the data acceptance timing. DDR SDRAM employs a data strobe signal (DQS) to notify the receiver of the data transfer timing. DQS is a bidirectional strobe signal and functions as the basic operating clock for DQ during read/write operations.

3.In the read cycle, DDR SDRAM drives the data strobe signal (DQS), which is in synchronization with the clock (CK). The receiver captures the data (DQ) using DQS as a timing reference.

4.In the write cycle, the controller drives the data strobe signal (DQS), which is in synchronization with the clock (CK).DDR SDRAM captures the data (DQ) using DQS as a timing reference.

5.Data is edge-aligned to DQS for read data and center-aligned for write data. This means that
when controller receives read data from DDR SDRAM, it will internally delay the received strobe
to the center of the received data window.